1. Field of the Invention
The invention relates to integrated circuit design, and in particular, to a layout method for standard cell placement on a system on chip.
2. Description of the Related Art
A system on chip (SOC) comprises thousands or millions of standard cells (also referred to as “cells”), such as logic units, AND gates, OR gates, and registers. Hence, an Electronic Design Automation (EDA) tool is required to help design an SOC. Conventionally, a floor plan (FLOOR PLAN) is performed to deposit analog modules, memory modules and IO pads on particular locations on the SOC. Other cells are then placed (PLACEMENT) on appropriate locations, and thereafter, a routing process (ROUTING) is performed.
FIG. 1a shows a conventional SOC 100. The SOC 100 has a height H and a width W, in which specific areas are already occupied by an analog module 112, a memory module 114 and IO pads 116. The placement of cells contains three types. The first type is a direct placement. The EDA tool directly places cells on standard cell region based on its operation frequency and connectivity relationships. For example, the R1 region in FIG. 1a is exactly the standard cell region that excludes the analog module 112 and the memory module 114. The second type is a specific reservation placement, whereby a particular region is reserved for a particular module according to user requirements, such as the R2 region in the SOC 100. The third type is an unspecific reservation placement. Area utilization rate of a particular region is regulated, but placement of cells is not constrained, such as the R3 region in the SOC 100.
When all cells are placed on the SOC 100, a routing and timing analysis is performed. The regions where routing resource are not enough, or where operation frequencies fail to meet a timing criterion, are marked as a light hotspot 104 or a heavy hotspot 106. If a region is not fully utilized, a plurality of free space 102 would be formed. A hotspot comprises two types based on its cause. One is a routing hotspot, wherein routing resource is not enough to accomplish wire connection between components. Another is a timing hotspot, wherein operation frequencies in the region cannot meet the timing criterion.
Hotspots always occur, and conventionally, chip area is recursively adjusted until all criteria for routing wires and operation frequencies are met. FIG. 1b is a flowchart of a conventional layout method. In step 101, the layout method is initialized. In step 103, a floor plan is performed on an SOC 100 with height H and width W. In step 105, the EDA tool performs a placement process based on the floor plan result to place cells of various types R1, R2 or R3 on the SOC 100. In step 107, the EDA tool performs a routing process on the SOC 100. In step 109, it is examined whether routing hotspots and timing hotspots have been mitigated. If any hotspot exists, step 111 is processed to increase the height H and width W of the SOC 100, and step 103 is repeated for a new floor plan. If all hotspots are mitigated, step 113 the layout method is concluded.
In practice, chip area is a limited resource, and mitigating the hotspots by enlarging chip area could induce considerable costs. Additionally, area utilization rate of non-hotspot areas are decreased when chip area is increased. Thus, the conventional approach is cost ineffective and produces less competitive products. Therefore an enhancement is desirable.